; ModuleID = '/Users/aserlili/Documents/Codes/llvm-build/test/OllvmTest/calculate.cpp'
source_filename = "/Users/aserlili/Documents/Codes/llvm-build/test/OllvmTest/calculate.cpp"
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "arm64-apple-macosx15.0.0"

%struct._opaque_pthread_once_t = type { i64, [8 x i8] }
%struct.StructTest = type { i32, ptr }

@once_flag = global %struct._opaque_pthread_once_t { i64 816954554, [8 x i8] zeroinitializer }, align 8
@.str = private unnamed_addr constant [22 x i8] c"This runs only once!\0A\00", align 1
@_ZL10once_flag2 = internal global %struct._opaque_pthread_once_t { i64 816954554, [8 x i8] zeroinitializer }, align 8
@.str.1 = private unnamed_addr constant [31 x i8] c"[calculate] a=%lf,b=%lf,op=%c\0A\00", align 1
@.str.2 = private unnamed_addr constant [25 x i8] c"struct_test str=%s,i=%d\0A\00", align 1
@_ZL11struct_test = internal constant %struct.StructTest { i32 2, ptr @.str.1 }, align 8

; Function Attrs: mustprogress noinline optnone ssp uwtable(sync)
define void @_Z13init_functionv() #0 {
entry:
  %call = call i32 (ptr, ...) @printf(ptr noundef @.str)
  ret void
}

declare i32 @printf(ptr noundef, ...) #1

; Function Attrs: mustprogress noinline optnone ssp uwtable(sync)
define noundef ptr @_Z11thread_funcPv(ptr noundef %arg) #0 {
entry:
  %arg.addr = alloca ptr, align 8
  store ptr %arg, ptr %arg.addr, align 8
  %call = call i32 @pthread_once(ptr noundef @once_flag, ptr noundef @_Z13init_functionv)
  ret ptr null
}

declare i32 @pthread_once(ptr noundef, ptr noundef) #1

; Function Attrs: mustprogress noinline optnone ssp uwtable(sync)
define void @_Z14init_function2v() #0 {
entry:
  %call = call i32 (ptr, ...) @printf(ptr noundef @.str)
  ret void
}

; Function Attrs: mustprogress noinline optnone ssp uwtable(sync)
define noundef ptr @_Z12thread_func2Pv(ptr noundef %arg) #0 {
entry:
  %arg.addr = alloca ptr, align 8
  store ptr %arg, ptr %arg.addr, align 8
  %call = call i32 @pthread_once(ptr noundef @_ZL10once_flag2, ptr noundef @_Z14init_function2v)
  ret ptr null
}

; Function Attrs: mustprogress noinline optnone ssp uwtable(sync)
define noundef double @_Z9calculateddc(double noundef %a, double noundef %b, i8 noundef signext %op) #0 {
entry:
  %conv1.reg2mem = alloca i32, align 4
  %retval = alloca double, align 8
  %a.addr = alloca double, align 8
  %b.addr = alloca double, align 8
  %op.addr = alloca i8, align 1
  store double %a, ptr %a.addr, align 8
  store double %b, ptr %b.addr, align 8
  store i8 %op, ptr %op.addr, align 1
  %0 = load double, ptr %a.addr, align 8
  %1 = load double, ptr %b.addr, align 8
  %2 = load i8, ptr %op.addr, align 1
  %conv = sext i8 %2 to i32
  %call = call i32 (ptr, ...) @printf(ptr noundef @.str.1, double noundef %0, double noundef %1, i32 noundef %conv)
  %3 = load i8, ptr %op.addr, align 1
  %conv1 = sext i8 %3 to i32
  store i32 %conv1, ptr %conv1.reg2mem, align 4
  %switchVar = alloca i64, align 8
  store i64 4520628922159550808, ptr %switchVar, align 8
  br label %loopEntry

loopEntry:                                        ; preds = %loopEnd, %entry
  %switchVar17 = load i64, ptr %switchVar, align 8
  br label %SwitchNode_L1_Main_

SwitchNode_L1_Main_:                              ; preds = %loopEntry
  %Pivot53 = icmp slt i64 %switchVar17, 4520628920612877472
  br i1 %Pivot53, label %SwitchNode_L2_Left_, label %SwitchNode_L2_Right_

SwitchNode_L2_Right_:                             ; preds = %SwitchNode_L1_Main_
  %Pivot52 = icmp slt i64 %switchVar17, 4520628922075026909
  br i1 %Pivot52, label %SwitchNode_L3_Left_40, label %SwitchNode_L3_Right_50

SwitchNode_L3_Right_50:                           ; preds = %SwitchNode_L2_Right_
  %Pivot51 = icmp slt i64 %switchVar17, 4520628922159550808
  br i1 %Pivot51, label %SwitchNode_L3_Leaf_42, label %SwitchNode_L4_Right_48

SwitchNode_L4_Right_48:                           ; preds = %SwitchNode_L3_Right_50
  %Pivot49 = icmp slt i64 %switchVar17, 4520628923545580350
  br i1 %Pivot49, label %SwitchNode_L4_Leaf_44, label %SwitchNode_L4_Leaf_46

SwitchNode_L4_Leaf_46:                            ; preds = %SwitchNode_L4_Right_48
  %SwitchLeaf47 = icmp eq i64 %switchVar17, 4520628923545580350
  br i1 %SwitchLeaf47, label %if.then, label %NewDefault

SwitchNode_L4_Leaf_44:                            ; preds = %SwitchNode_L4_Right_48
  %SwitchLeaf45 = icmp eq i64 %switchVar17, 4520628922159550808
  br i1 %SwitchLeaf45, label %first, label %NewDefault

SwitchNode_L3_Leaf_42:                            ; preds = %SwitchNode_L3_Right_50
  %SwitchLeaf43 = icmp eq i64 %switchVar17, 4520628922075026909
  br i1 %SwitchLeaf43, label %if.else5, label %NewDefault

SwitchNode_L3_Left_40:                            ; preds = %SwitchNode_L2_Right_
  %Pivot41 = icmp slt i64 %switchVar17, 4520628920828298778
  br i1 %Pivot41, label %SwitchNode_L3_Leaf_32, label %SwitchNode_L4_Right_38

SwitchNode_L4_Right_38:                           ; preds = %SwitchNode_L3_Left_40
  %Pivot39 = icmp slt i64 %switchVar17, 4520628921956336573
  br i1 %Pivot39, label %SwitchNode_L4_Leaf_34, label %SwitchNode_L4_Leaf_36

SwitchNode_L4_Leaf_36:                            ; preds = %SwitchNode_L4_Right_38
  %SwitchLeaf37 = icmp eq i64 %switchVar17, 4520628921956336573
  br i1 %SwitchLeaf37, label %if.else9, label %NewDefault

SwitchNode_L4_Leaf_34:                            ; preds = %SwitchNode_L4_Right_38
  %SwitchLeaf35 = icmp eq i64 %switchVar17, 4520628920828298778
  br i1 %SwitchLeaf35, label %if.else, label %NewDefault

SwitchNode_L3_Leaf_32:                            ; preds = %SwitchNode_L3_Left_40
  %SwitchLeaf33 = icmp eq i64 %switchVar17, 4520628920612877472
  br i1 %SwitchLeaf33, label %if.else16, label %NewDefault

SwitchNode_L2_Left_:                              ; preds = %SwitchNode_L1_Main_
  %Pivot31 = icmp slt i64 %switchVar17, 4520628919919980967
  br i1 %Pivot31, label %SwitchNode_L3_Left_, label %SwitchNode_L3_Right_

SwitchNode_L3_Right_:                             ; preds = %SwitchNode_L2_Left_
  %Pivot30 = icmp slt i64 %switchVar17, 4520628920277400015
  br i1 %Pivot30, label %SwitchNode_L3_Leaf_22, label %SwitchNode_L4_Right_28

SwitchNode_L4_Right_28:                           ; preds = %SwitchNode_L3_Right_
  %Pivot29 = icmp slt i64 %switchVar17, 4520628920494837245
  br i1 %Pivot29, label %SwitchNode_L4_Leaf_24, label %SwitchNode_L4_Leaf_26

SwitchNode_L4_Leaf_26:                            ; preds = %SwitchNode_L4_Right_28
  %SwitchLeaf27 = icmp eq i64 %switchVar17, 4520628920494837245
  br i1 %SwitchLeaf27, label %if.then12, label %NewDefault

SwitchNode_L4_Leaf_24:                            ; preds = %SwitchNode_L4_Right_28
  %SwitchLeaf25 = icmp eq i64 %switchVar17, 4520628920277400015
  br i1 %SwitchLeaf25, label %if.then14, label %NewDefault

SwitchNode_L3_Leaf_22:                            ; preds = %SwitchNode_L3_Right_
  %SwitchLeaf23 = icmp eq i64 %switchVar17, 4520628919919980967
  br i1 %SwitchLeaf23, label %return, label %NewDefault

SwitchNode_L3_Left_:                              ; preds = %SwitchNode_L2_Left_
  %Pivot21 = icmp slt i64 %switchVar17, 4520628919787516219
  br i1 %Pivot21, label %SwitchNode_L3_Leaf_, label %SwitchNode_L4_Right_

SwitchNode_L4_Right_:                             ; preds = %SwitchNode_L3_Left_
  %Pivot = icmp slt i64 %switchVar17, 4520628919883304070
  br i1 %Pivot, label %SwitchNode_L4_Leaf_, label %SwitchNode_L4_Leaf_19

SwitchNode_L4_Leaf_19:                            ; preds = %SwitchNode_L4_Right_
  %SwitchLeaf20 = icmp eq i64 %switchVar17, 4520628919883304070
  br i1 %SwitchLeaf20, label %if.then4, label %NewDefault

SwitchNode_L4_Leaf_:                              ; preds = %SwitchNode_L4_Right_
  %SwitchLeaf18 = icmp eq i64 %switchVar17, 4520628919787516219
  br i1 %SwitchLeaf18, label %if.then8, label %NewDefault

SwitchNode_L3_Leaf_:                              ; preds = %SwitchNode_L3_Left_
  %SwitchLeaf = icmp eq i64 %switchVar17, 4520628919642824465
  br i1 %SwitchLeaf, label %if.else15, label %NewDefault

NewDefault:                                       ; preds = %SwitchNode_L4_Leaf_46, %SwitchNode_L4_Leaf_44, %SwitchNode_L3_Leaf_42, %SwitchNode_L4_Leaf_36, %SwitchNode_L4_Leaf_34, %SwitchNode_L3_Leaf_32, %SwitchNode_L4_Leaf_26, %SwitchNode_L4_Leaf_24, %SwitchNode_L3_Leaf_22, %SwitchNode_L4_Leaf_19, %SwitchNode_L4_Leaf_, %SwitchNode_L3_Leaf_
  br label %switchDefault

switchDefault:                                    ; preds = %NewDefault
  br label %loopEnd

first:                                            ; preds = %SwitchNode_L4_Leaf_44
  %conv1.reload = load i32, ptr %conv1.reg2mem, align 4
  %cmp = icmp eq i32 %conv1.reload, 43
  %4 = sub i64 0, -4520628923545580350
  %5 = sub i64 0, -4520628920828298778
  %6 = select i1 %cmp, i64 %4, i64 %5
  store i64 %6, ptr %switchVar, align 8
  br label %loopEnd

if.then:                                          ; preds = %SwitchNode_L4_Leaf_46
  %7 = load double, ptr %a.addr, align 8
  %8 = load double, ptr %b.addr, align 8
  %add = fadd double %7, %8
  store double %add, ptr %retval, align 8
  %9 = sub i64 0, -4520628919919980967
  store i64 %9, ptr %switchVar, align 8
  br label %loopEnd

if.else:                                          ; preds = %SwitchNode_L4_Leaf_34
  %10 = load i8, ptr %op.addr, align 1
  %conv2 = sext i8 %10 to i32
  %cmp3 = icmp eq i32 %conv2, 45
  %11 = sub i64 0, -4520628919883304070
  %12 = sub i64 0, -4520628922075026909
  %13 = select i1 %cmp3, i64 %11, i64 %12
  store i64 %13, ptr %switchVar, align 8
  br label %loopEnd

if.then4:                                         ; preds = %SwitchNode_L4_Leaf_19
  %14 = load double, ptr %a.addr, align 8
  %15 = load double, ptr %b.addr, align 8
  %sub = fsub double %14, %15
  store double %sub, ptr %retval, align 8
  %16 = sub i64 0, -4520628919919980967
  store i64 %16, ptr %switchVar, align 8
  br label %loopEnd

if.else5:                                         ; preds = %SwitchNode_L3_Leaf_42
  %17 = load i8, ptr %op.addr, align 1
  %conv6 = sext i8 %17 to i32
  %cmp7 = icmp eq i32 %conv6, 42
  %18 = sub i64 0, -4520628919787516219
  %19 = sub i64 0, -4520628921956336573
  %20 = select i1 %cmp7, i64 %18, i64 %19
  store i64 %20, ptr %switchVar, align 8
  br label %loopEnd

if.then8:                                         ; preds = %SwitchNode_L4_Leaf_
  %21 = load double, ptr %a.addr, align 8
  %22 = load double, ptr %b.addr, align 8
  %mul = fmul double %21, %22
  store double %mul, ptr %retval, align 8
  %23 = sub i64 0, -4520628919919980967
  store i64 %23, ptr %switchVar, align 8
  br label %loopEnd

if.else9:                                         ; preds = %SwitchNode_L4_Leaf_36
  %24 = load i8, ptr %op.addr, align 1
  %conv10 = sext i8 %24 to i32
  %cmp11 = icmp eq i32 %conv10, 47
  %25 = sub i64 0, -4520628920494837245
  %26 = sub i64 0, -4520628920612877472
  %27 = select i1 %cmp11, i64 %25, i64 %26
  store i64 %27, ptr %switchVar, align 8
  br label %loopEnd

if.then12:                                        ; preds = %SwitchNode_L4_Leaf_26
  %28 = load double, ptr %b.addr, align 8
  %cmp13 = fcmp une double %28, 0.000000e+00
  %29 = sub i64 0, -4520628920277400015
  %30 = sub i64 0, -4520628919642824465
  %31 = select i1 %cmp13, i64 %29, i64 %30
  store i64 %31, ptr %switchVar, align 8
  br label %loopEnd

if.then14:                                        ; preds = %SwitchNode_L4_Leaf_24
  %32 = load double, ptr %a.addr, align 8
  %33 = load double, ptr %b.addr, align 8
  %div = fdiv double %32, %33
  store double %div, ptr %retval, align 8
  %34 = sub i64 0, -4520628919919980967
  store i64 %34, ptr %switchVar, align 8
  br label %loopEnd

if.else15:                                        ; preds = %SwitchNode_L3_Leaf_
  store double -1.000000e+00, ptr %retval, align 8
  %35 = sub i64 0, -4520628919919980967
  store i64 %35, ptr %switchVar, align 8
  br label %loopEnd

if.else16:                                        ; preds = %SwitchNode_L3_Leaf_32
  store double -1.000000e+00, ptr %retval, align 8
  %36 = sub i64 0, -4520628919919980967
  store i64 %36, ptr %switchVar, align 8
  br label %loopEnd

return:                                           ; preds = %SwitchNode_L3_Leaf_22
  %37 = load double, ptr %retval, align 8
  ret double %37

loopEnd:                                          ; preds = %if.else16, %if.else15, %if.then14, %if.then12, %if.else9, %if.then8, %if.else5, %if.then4, %if.else, %if.then, %first, %switchDefault
  br label %loopEntry
}

; Function Attrs: mustprogress noinline norecurse optnone ssp uwtable(sync)
define noundef i32 @main(i32 noundef %argc, ptr noundef %argv) #2 {
entry:
  %retval = alloca i32, align 4
  %argc.addr = alloca i32, align 4
  %argv.addr = alloca ptr, align 8
  store i32 0, ptr %retval, align 4
  store i32 %argc, ptr %argc.addr, align 4
  store ptr %argv, ptr %argv.addr, align 8
  %0 = load ptr, ptr getelementptr inbounds (%struct.StructTest, ptr @_ZL11struct_test, i32 0, i32 1), align 8
  %call = call i32 (ptr, ...) @printf(ptr noundef @.str.2, ptr noundef %0, i32 noundef 2)
  %call1 = call noundef double @_Z9calculateddc(double noundef 0.000000e+00, double noundef 0.000000e+00, i8 noundef signext 47)
  %call2 = call noundef double @_Z9calculateddc(double noundef 1.000000e+00, double noundef 2.000000e+00, i8 noundef signext 47)
  %call3 = call noundef double @_Z9calculateddc(double noundef 1.000000e+00, double noundef 2.000000e+00, i8 noundef signext 43)
  %call4 = call noundef double @_Z9calculateddc(double noundef 1.000000e+00, double noundef 2.000000e+00, i8 noundef signext 45)
  ret i32 0
}

attributes #0 = { mustprogress noinline optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
attributes #1 = { "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
attributes #2 = { mustprogress noinline norecurse optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }

!llvm.module.flags = !{!0, !1, !2, !3, !4}
!llvm.ident = !{!5}

!0 = !{i32 2, !"SDK Version", [2 x i32] [i32 15, i32 5]}
!1 = !{i32 1, !"wchar_size", i32 4}
!2 = !{i32 8, !"PIC Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 1}
!4 = !{i32 7, !"frame-pointer", i32 1}
!5 = !{!"clang version 19.1.3 (git@github.com:zylc369/Arkari.git ef2500cb061e3b3f97cea27f8f8127a5478075b3)"}
